This invention generally relates to methods for reducing corrosive contamination on semiconductor surfaces and more particularly to reducing fluorine contamination induced defects on bonding pad surfaces.
In semiconductor fabrication, various layers of insulating material, semiconducting material and conducting material are formed to produce a multilayer semiconductor device. The layers are patterned to create features that taken together, form elements such as transistors, capacitors, and resistors. These elements are then interconnected to achieve a desired electrical function, thereby producing an integrated circuit (IC) device. The formation and patterning of the various device layers are achieved using conventional fabrication techniques, such as oxidation, implantation, deposition, epitaxial growth of silicon, lithography, etching, and planarization.
In a typical multilayer semiconductor device the uppermost layers which are electrically interconnected with underlying layers by way of, for example, vias, additionally include bonding pads for forming electrical connection with the semiconductor device (chip) surface to a package which contains the chip. The bonding pads are typically formed in an array on the semiconductor wafer surface which similarly includes an array of devices or chips.
Prior to cutting the semiconductor wafer into the various constituent chips, the semiconductor wafer surface including the bonding pads are covered with one or more passivation layers to insulate conducting areas and to physically protect the chip surface. Dielectrics, for example making various layers of the semiconductor device, are adversely affected by moisture. For example, some of the adverse affects include, reduction of bulk resistivity, electrical polarization effects, hot electron effects, and slow trapping degradation. Dielectric materials are also affected mechanically in that they tend to expand and exert compressive stresses as they absorb moisture. Dielectric materials may also be chemically attacked by moisture, for example when doped with boron and phosphorus. Formation of boric and phosphoric acids can result and initiate corrosion of surrounding interconnect materials.
In order to prevent moisture build-up and penetration in the device, one or more passivation layers are formed on the surface of the device. The passivation layer is typically patterned to form openings over the bonding pads to which bond wires are subsequently connected. The passivation layer also protects the semiconductor surface from conductive particles and scratches causing, for example, shorts of conductive interconnects at the device surface.
In a typical method for applying a passivation layer, a first passivation layer is typically formed by chemical vapor deposition (CVD), for example by PECVD (plasma enhanced CVD) forming a blanket layer over the process wafer surface including the bonding pads, for example copper or aluminum. The first passivation layer, for example is a dielectric such as silicon nitride (e.g. Si3N4, SiXNiY, HZ,) forming a layer typically 7000-12000 Angstroms thick over the underlying metallic bonding pads, which are typically 4000-8000 Angstroms in thickness.
Following deposition of the first passivation layer, another dielectric passivation layer may optionally be applied. Following the application of dielectric passivation layers, a layer of photoresist is deposited to photolithographically pattern the dielectric passivation layers for reactive ion etching to expose an area overlying the bonding pads. The photoresist layer forms an overlying, thicker passivation layer, for example, a photosensitive polyimide, providing additional insulation and physical protection for the semiconductor device. Recently, it has been the practice to leave the photoresist layer, for example a photosensitive polyimide, as a second passivation layer on the process wafer surface after patterning and etching an opening through the first passivation layer over the bonding pads. A polyimide resin is excellent in electrical and mechanical characteristics, including high heat resistance and is advantageously used as a surface-protecting and insulation layer for a semiconductor device. Following formation of the passivation layers, the semiconductor wafer is tested, diced into individual chips, the chips mounted in chip carrier packages and the bond pads electrically connected to the chip carrier package.
One problem in the prior art method of passivation layer application and patterning, and reactively ion etching to expose the bonding pad surface is fluorine contamination from the reactive ion etching process. For example hydrofluorocarbon containing plasmas are routinely used to etch metal nitrides, including a silicon nitride passivation layer overlying a bonding pad surface. The issue of fluorine contamination is particularly problematic with aluminum bonding pads where over time, for example after period of storage of the chips in plastic boxes, the fluorine contamination on a wafer may tend to segregate out to corrode the bonding pad surface or to form fluorinated aluminum crystallites on the bonding pad surface. As a result, bonding to the bonding pad surfaces exhibit a high rate of failure due to reduced adhesion of the wire bond to the bonding pad surface.
The use of the polyimide photoresist as an uppermost passivation layer tends to exacerbate the problem of fluorine contamination since it readily collects fluorine contamination.
Therefore, there is a need in the semiconductor art to develop a process whereby fluorine contamination remaining following a reactive ion etching process is removed from a semiconductor wafer surface such that long term effects including segregation onto bonding pad surfaces is avoided thereby increasing a yield of packaged semiconductor chips.
It is therefore an object of the invention to provide a process whereby fluorine contamination remaining following a reactive ion etching process is removed from a semiconductor wafer surface such that long term effects including segregation onto bonding pad surfaces is avoided thereby increasing a yield of packaged semiconductor chips while overcoming other shortcomings and deficiencies in the prior art.
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method for reducing a fluorine contamination level on a semiconductor wafer process surface.
In one embodiment of the present invention, the method includes providing a semiconductor wafer surface having a process surface including an uppermost polyimide containing layer; reactive ion etching the process surface to include exposure of the process surface to a hydrofluorocarbon containing plasma; and, heating the process surface according to a temperature profile to reduce a fluorine contamination level.
In related embodiments the temperature profile includes a temperature of from about 200 degrees Centigrade to about 350 degrees Centigrade. Further, the temperature profile includes heating time periods of from about 1 hour to about 6 hours. Further yet, the temperature profile includes at least one of a temperature heating rate and a temperature soaking time.
In another embodiment, the step of heating is carried out under controlled ambient conditions.
In other embodiments the polyimide containing layer comprises a photosensitive passivation layer overlying bonding pad surfaces. Further, the polyimide containing layer is photolithographically patterned and developed to reveal an underlying passivation layer prior to the step of reactive ion etching. Further yet, the step of reactive ion etching further includes etching through at least one underlying passivation layer to reveal bonding pad surfaces.
In another embodiment, the bonding pad surfaces include one of aluminum and copper.
In yet another embodiment, the method further comprises the step of storing the semiconductor wafer under controlled ambient conditions.